Juried Engineering CD4026BE CD4026 CD4026 CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable Breadboard-Friendly IC

Juried Engineering CD4026BE CD4026 CD4026 CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable Breadboard-Friendly IC

The CD4026B consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display Counter and 7-segment decoding in one package, Easily interfaced with 7-segment display types, Standardized, symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings Fully static counter operation: DC to 6 MHz (typ.) at VDD = 10 V, 100% tested for quiescent current at 20 V Ideal for low-power displays, Display enable output, Schmitt-triggered clock inputs, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices" Example Applications: Decade counting 7-segment decimal display, Frequency division 7-segment decimal displays, Clocks, watches, timers (e.g. ÷60, ÷60, ÷ 12 counter/display), Counter/display driver for meter applications, LED driver The CD4026B consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display.

These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important.

Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs.

A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on high when the DISPLAY ENABLE IN is high.